The present invention relates to a semiconductor storage device and, more particularly, to a technique especially effective for use in a dynamic RAM having a plurality of memory arrays.
There is the so-called one-bit output type dynamic RAM having a plurality of memory arrays and adapted to selectively provide signals from such memory arrays through an output terminal. Such a dynamic RAM is provided with a set of complementary common data lines corresponding to each memory array and a main amplifier corresponding to each set of the complementary common data lines.
As to the aforesaid one-bit output type dynamic RAM, descriptions are given, for example, in "HITACHI IC Memory Data Book", pages 314-320, issued by Hitachi, Ltd. in September, 1983.
With the progress in technology to provide larger capacity in such a dynamic RAM and from the resulted necessity for securing quantities of read out signal from the memory cells to be output to the data lines, such a method is employed that the memory array is divided in the extended direction of the data line. In FIG. 5 is shown a block diagram of a large-capacity dynamic RAM developed by the inventor in the present application prior to this invention. In this dynamic RAM, there are provided eight memory arrays M0-M7 and eight main amplifiers MA0-MA7 disposed adjacent to their corresponding memory arrays. There are also provided complementary common input/output lines CIO, CIO for connecting each of the main amplifiers and the data input/output circuit I/O and connection circuits S0-S7 for selectively connecting the complementary common input/output lines CIO, CIO and one of the main amplifiers corresponding to a specified address.
As such a dynamic RAM has become larger in its capacity, the time required for testing the memory cells has increased, and therefore, there has been proposed the multi-bit testing mode in which the same test data have been written into plural memory cells disposed at the same address of the plural memory arrays and these test data are read out simultaneously and are checked. The dynamic RAM having such a testing function is provided with a testing logical circuit TL as shown in FIG. 5. Since the testing logical circuit TL is supplied with the data simultaneously read out from the eight main amplifiers MA0-MA7, the testing logical circuit TL is provided, other than the aforesaid complementary common input/output lines CIO, CIO, with complementary signal lines connecting the same and each of the main amplifiers. Therefore, the space required for accommodating these complementary lines becomes larger and the layout around the testing logical circuit becomes more complex and as a result the chip size becomes larger.